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1/12 july 2001 n high speed: f max = 84mhz (typ.) at v cc = 6v n low power dissipation: i cc = 4 m a(max.) at t a =25c n high noise immunity: v nih = v nil = 28 % v cc (min.) n symmetrical output impedance: |i oh | = i ol =6ma (min) n balanced propagation delays: t plh @ t phl n wide operating voltage range: v cc (opr) = 2v to 6v n pin and function compatible with 74 series 173 description the m74hc173 is an high speed cmos quad d-type register (3-state) fabricated with silicon gate c 2 mos technology. this device is composed of a four-bit register including d-type flip-flops and 3-state buffers. the four flip-flops are controlled by a common clock input (clock) and a common reset input (clear). signals applied to the data inputs (d 1 - d 4 ) are stored at the respective flip-flops on the positive going transition of the clock input, only when both clock control inputs (g1 and g2) are held low. the reset feature is asynchronous and active high. the stored data are provided on each output only when both output control inputs (m and n) are held low, otherwise the outputs go to the high-impedance state. all inputs are equipped with protection circuits against static discharge and transient excess voltage. m74hc173 quad d-type register (3 state) pin connection and iec logic symbols order codes package tube t & r dip m74hc173b1r sop m74hc173m1r M74HC173RM13TR tssop m74hc173ttr tssop dip sop
m74hc173 2/12 input and output equivalent circuit pin description truth table x : dont care z : high impedance pin no symbol name and function 1, 2 m, n output enable input (active low) 3, 4, 5, 6 1q to 4q 3-state flip-flop outputs 7 clock clock input (low to high, edge-triggered) 9, 10 g1, g2 data enable inputs (active low) 14, 13, 12, 11 1d to 4d data inputs 15 clear asynchronous master reset (active high) 8 gnd ground (0v) 16 v cc positive supply voltage clear clock data enable dn output control qn g1 g2 m n xxxxxhxz xxxxxxhz hxxxxll l l xxxllq0 lhxxllq0 l xhxl lq0 lllhllh l llllll
m74hc173 3/12 logic diagram this logic diagram has not be used to estimate propagation delays absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied (*) 500mw at 65 c; derate to 300mw by 10mw/ c from 65 c to 85 c symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 35 ma i cc or i gnd dc v cc or ground current 70 ma p d power dissipation 500(*) mw t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c
m74hc173 4/12 recommended operating conditions dc specifications symbol parameter value unit v cc supply voltage 2 to 6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c t r , t f input rise and fall time v cc = 2.0v 0 to 1000 ns v cc = 4.5v 0 to 500 ns v cc = 6.0v 0 to 400 ns symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 v il low level input voltage 2.0 0.5 0.5 0.5 v 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 v oh high level output voltage 2.0 i o =-20 m a 1.9 2.0 1.9 1.9 v 4.5 i o =-20 m a 4.4 4.5 4.4 4.4 6.0 i o =-20 m a 5.9 6.0 5.9 5.9 4.5 i o =-4.0 ma 4.18 4.31 4.13 4.10 6.0 i o =-5.2 ma 5.68 5.8 5.63 5.60 v ol low level output voltage 2.0 i o =20 m a 0.0 0.1 0.1 0.1 v 4.5 i o =20 m a 0.0 0.1 0.1 0.1 6.0 i o =20 m a 0.0 0.1 0.1 0.1 4.5 i o =4.0 ma 0.17 0.26 0.33 0.40 6.0 i o =5.2 ma 0.18 0.26 0.33 0.40 i i input leakage current 6.0 v i = v cc or gnd 0.1 1 1 m a i oz high impedance output leakage current 6.0 v i = v ih or v il v o = v cc or gnd 0.5 5.0 10 m a i cc quiescent supply current 6.0 v i = v cc or gnd 44080 m a
m74hc173 5/12 ac electrical characteristics (c l = 50 pf, input t r = t f = 6ns) symbol parameter test condition value unit v cc (v) c l (pf) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t tlh t thl output transition time 2.0 50 25 60 75 90 ns 4.5 7121518 6.0 6101315 t plh t phl propagation delay time (clock - q) 2.0 50 50 115 145 175 ns 4.5 14 23 29 35 6.0 12 20 25 30 2.0 150 65 145 180 220 ns 4.5 18 29 36 44 6.0 15 25 31 37 t plh t phl propagation delay time (clear - q) 2.0 50 50 115 145 175 ns 4.5 14 23 29 35 6.0 12 20 25 30 2.0 150 65 145 180 220 ns 4.5 18 29 36 44 6.0 15 25 31 37 f max maximum clock frequency 2.0 50 8.6 20 6.8 5.8 mhz 4.5 43 67 34 29 6.0 51 84 40 34 t pzl t pzh output enable time 2.0 50 r l = 1 k w 50 115 145 175 ns 4.5 14 23 29 35 6.0 12 20 25 30 2.0 150 r l = 1 k w 65 145 180 220 ns 4.5 18 29 36 44 6.0 15 25 31 37 t plz t phz output disable time 2.0 50 r l = 1 k w 36 105 130 160 ns 4.5 15 21 26 32 6.0 13 18 22 27 t w(h) t w(l) minimum pulse width (clock) 2.0 50 16 75 95 110 ns 4.5 4151922 6.0 3131619 t w(l) minimum pulse width (clear) 2.0 50 16 75 95 110 ns 4.5 4151922 6.0 3131619 t s minimum set-up time (g1, g2) 2.0 50 40 100 125 150 ns 4.5 10 20 25 30 6.0 9172126 t s minimum set-up time (d) 2.0 50 24 75 95 110 ns 4.5 6151922 6.0 5131619 t h minimum hold time (g1 ,g2, d) 2.0 50 000 ns 4.5 0 0 0 6.0 0 0 0 t rem minimum removal time 2.0 50 555 ns 4.5 5 5 5 6.0 5 5 5
m74hc173 6/12 capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /4 (per circuit) test circuit c l = 50pf/150pf or equivalent (includes jig and probe capacitance) r 1 = 1k w or equivalent r t = z out of pulse generator (typically 50 w ) symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 5.0 5101010pf c pd power dissipation capacitance (note 1) 5.0 50 pf test switch t plh , t phl open t pzl , t plz v cc t pzh , t phz gnd
m74hc173 7/12 waveform 1: propagation delay times, minimum pulse width (clock), setup and hold time (dn to clock) (f=1mhz; 50% duty cycle) waveform 2: minimum pulse width (clear) an dremoval time (clear to clock) (f=1mhz; 50% duty cycle)
m74hc173 8/12 waveform 3: output enable and disable time (f=1mhz; 50% duty cycle) waveform 4: input waveforms (f=1mhz; 50% duty cycle)
m74hc173 9/12 dim. mm. inch min. typ max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 plastic dip-16 (0.25) mechanical data p001c
m74hc173 10/12 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data po13h
m74hc173 11/12 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
m74hc173 12/12 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com

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